A clock-tuning circuit for system-on-chip

In SoC design, multiple buffered clock distribution networks are typically used to drive the large clock loads of the different clock domains. Chip design involves a clock alignment step, which equalizes the delay from the clock source to each and every flop. Accurate clock alignment is important, because unwanted differences or uncertainties in clock network delays may degrade performance or cause functional errors. Clock distribution and alignment has become an increasingly challenging problem in VLSI design, consuming an increasing portion of resources such as wiring area, power and design time. Ideally, IP cores should be treated as “black-boxes” to support a modular design methodology, in which IP cores can be inserted or removed without affecting other blocks. However, the clock distribution network does not support this concept because each change influences the complete network (as well as the other networks of unrelated clocks). Redesign and verification of global clock distribution networks may be required after each change. Such iterations are undesirable and should be minimized. For hard IP cores, clock routing is carried out during the design of the IP core. The timing interface between the hard IP core and the rest of the SoC (signal setup and hold times, input capacitance) must be carefully considered. A change of a hard IP core might necessitate a complete redesign of the clock network. For soft IP cores, clock tree routing is performed during chip level integration. Clock distribution and alignment within soft IP cores become the responsibility of the system integrator. A similar problem exists with soft macros which had already been placed and routed, and consequently engineers are reluctant to re-design them. In a competitive commercial environment, IC design is typically optimized for shortest time to market. To shorten design times, physical design is often performed in parallel with logic design, although in theory the former should follow the completion of the latter. In such cases, global physical features of the IC, such as the global clock distribution networks, may have to be redesigned multiple times, where each change in the logic incurs painful and expensive redo of the global nets. Clock tuning can be used to eliminate repetitive redesign of the clock network. High-speed systems with multiple boards often require clock tuning after assembly. A tuning circuit can be used statically or dynamically to perform clock alignment according to the uncertainty of the system. Multiple PLLs may be employed to align the clock dynamically, but are expensive and difficult to design. We have developed a novel and efficient method for clock alignment in SoC design, using a programmable circuit for static delay tuning. The main goals of the static delay tuning are to enable quick and easy integration of IP cores into SoC and to ease the design of the clock distribution network of the SoC. First we demonstrate the problem of IP core integration due to different clock delays. Next, the common solution of signal delay insertion is described and its inefficiency is discussed. The preferred method of clock delay insertion is presented afterwards, using either global clock redesign or tuning. Later we describe variants of clock tuning and analysis of clock skew. The final sections present circuits, experimental results, and conclusions. The method has been applied to a commercial multi-standard demodulator and decoder chip for terrestrial and cable Digital and analog TV TV reception. The chip contains 12M devices, and has been fabricated using a 0.18μm CMOS technology. The method has saved many weeks of design time (relative to a previous similar design) and the circuits worked flawlessly on first silicon. Our method was inspired by Globally Asynchronous, Locally Synchronous (GALS) architecture. As SoCs grow larger and faster, and integrate more clock domains of different frequencies, clock tuning methods will be replaced by asynchronous interconnects.